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| corecfi handbook v2.0
actel corporation, mountain view, ca 94043 ? 2007 actel corporation. all rights reserved. printed in the united states of america part number: 50200094-0 release: march 2007 no part of this document may be copied or reproduced in any form or by any means without prior written consent of actel. actel makes no warranties with respect to this do cumentation and disclaims any implied warranties of merchantability or fitness for a particular purpose. information in this document is subject to change without notice. actel assumes no responsibility for any errors that may appear in this document. this document contains confidential proprietary information that is not to be disclosed to any unauthorized person without prior written consent of actel corporation. trademarks actel and the actel logo are registered trademarks of actel corporation. adobe and acrobat reader are registered trademarks of adobe systems, inc. all other products or brand names mentioned are tradem arks or registered trademarks of their respective holders. corecfi handbook v2.0 3 table of contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 core overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 device utilization and performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 tool flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 coreconsole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 importing into libero ide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 simulation flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 synthesis in libero ide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 place-and-route in libero ide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 supported cfi commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 read query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 read id codes command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 read array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 read status command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 clear status command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 erase page command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 single write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 multi-write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 page lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 page unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5 implementation hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 usage with internal flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 generating and programming the cfi query database . . . . . . . . . . . . . . . . . . . . . . 35 6 testbench operation and modification . . . . . . . . . . . . . . . . . . . . . 39 verification testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 simple application testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 a vhdl testbench support routines . . . . . . . . . . . . . . . . . . . . . . . 41 table of contents 4 corecfi handbook v2.0 b product support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 customer service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 actel customer technical support center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 actel technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 contacting the customer technical support center . . . . . . . . . . . . . . . . . . . . . . . . 43 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 corecfi handbook v2.0 5 introduction core overview corecfi (common flash interface) provides an industry standard external interface to the embedded flash memory blocks within the fusion family of actel devices. using corecfi, the user is able to communicate (i.e., read, write, and erase) with the embedded flash memory. this ip block is ta rgeted to provide a functional subset of corecfi with a design emphasis given to minimizing design size. note th at this handbook focuses on the operation of corecfi and does not provide detail on the structure or the behavior of the fusion flash memory. refer to the fusion family of mixed-signal flash fpgas datasheet for details on the fusion flash memory. note that corecfi has been designed to be used with an external device, though it can be adapted for use with user-created custom logic within the fusion fpga fabric. corecfi has two top-level parameters (verilog) or generics (vhdl) used to configure the core. for a detailed description of the parameters/generics, refer to table 3-1 on page 11 . corecfi block diagram is shown in figure 1 . a typical application using corecfi is shown in figure 2 on page 6 . note that the d pin output enable signal is inverted. figure 1 corecfi block diagram fm_address[17:0] fm_data_in[31:0] fm_data_width[1:0] fm_data_out[31:0] fm_status[1:0] fm_read fm_write fm_program fm_erase_page fm_overwrite_protect fm_unprotect_page fm_discard_page fm_spare_page fm_page_status fm_busy dq_oe_n byte_n word_n ce_n oe_n we_n rp_n ry_by_n a[17:0] dq_in[31:0] dq_out[31:0] cfi interface fsm clk cfi interface flash memory interface flash memory control logic corecfi introduction 6 corecfi handbook v2.0 figure 2 corecfi typical application device utilization and performance corecfi has been implemented in the actel fusion tm device family. a summary of the device utilization for corecfi is listed in table 1 and table 2 . fusion fpga external cpu a[17:0] d[31:0] corecfi fusion flash memory flash memory interface a[17:0] d_in[31:0] d_out[31:0] dq_oe_n ce_n oe_n we_n byte_n word_n rp_n ry_by_n table 1 corecfi device utilization an d performance (minimum configuration) family cells or tiles device utilization performance sequential combinatorial total fusion 175 294 469 afs090 20% 100 mhz note: data in this table was achieved using typical synthesis and layout settings. top-level parameters/generics that differ from the default values were set as follows: size = 8. table 2 corecfi device utilization and performance (maximum configuration) family cells or tiles device utilization performance sequential combinatorial total fusion 177 306 483 afs090 21% 100 mhz note: data in this table was achieved using typical synthesis and layout settings. top-level parameters/generics that differ from the default values were set as follows: size = 18. corecfi handbook v2.0 7 1 functional description the corecfi design is primarily a state machine that cont rols the interfaces to the fusion flash memory and the external cfi interface. corecfi implements a subset of the common flash memory interface specification release 2.0. it supports the following: ? read and read query, automatic write and erase, lock, and status operations ? 128-byte write page buffer and write/erase size ? 16-byte page read buffer ? 8-bit, 16-bit, and 32-bit operation corecfi handbook v2.0 9 2 tool flows licenses corecfi is licensed in three ways; depending on yo ur license tool flow, functionality may be limited. evaluation the precompiled simulation libraries prov ided allow the core to be instantiated in coreconsole and simulated within actel libero ? integrated design environment (ide) as described in simulation flows on page 10 . the design cannot be synthesized, as the source code is not provided. obfuscated complete rtl code is provided for the core, enabling the core to be instantiated with coreconsole. simulation, synthesis, and layout can be performed with libero ide. the rtl code for the core is obfuscated, and some of the testbench source files are not provided. instead, they are precompiled into the compiled simulation library. rtl complete rtl source code is prov ided for the core and testbenches. coreconsole corecfi is preinstalled in the coreconsole ip deployment platform (idp). to use the core, 1 click and drag it from the ip core list into the main window. the core can then be configured using the configuration gui within coreconsole, as shown in figure 2-1 and figure 2-2 on page 10 . the coreconsole project can be exported to libero ide at this point, providing access just to corecfi, or othe r ip blocks can be interconnected, allowing the complete system to be exported from coreconsole to libero ide. figure 2-1 corecfi configuration within coreconsole 1. a corecfi license is required to ge nerate the design for export to libe ro ide for simulation and synthesis . tool flows 10 corecfi handbook v2.0 figure 2-2 corecfi configuration with in coreconsole ? testbench selection importing into libero ide after generating and exporting the core from coreconsole, the core can be imported into libero ide. create a new project in libero ide and import the coreconsole project from the liberoexport directory. libero ide will then install the core and the selected testbenches, along with constraints and documentation, into its project. note: if two or more directcores are required, they can both be included in the same coreconsole project and imported into libero ide at the same time. simulation flows to run simulations, the required testbench flow must be selected within coreconsole, then save & generate must be run from the generate pane. the required testbench is selected through the core testbench configuration gui. two simulation testbenches are supported with corecfi: ? simple corecfi application testbench (vhdl and verilog) ? full corecfi verification testbench (vhdl only) when coreconsole generates the libero ide project, it will install the appropriate testbench files. to run either the simple application or the full verification environment, simply set the design root to the corecfi instantiation in the libero ide design hierarchy and click the simulation icon in the libero design flow window. this will invoke model sim ? and automatically run the simulation. synthesis in libero ide having set the design root appropriately, click the synthesis icon in libero ide. the synthesis window appears, displaying the synplicity? project. set synplicity to use the verilog 2001 standard if verilog is being used. to run synthesis, click the run icon. place-and-route in libero ide having set the design root appropr iately and run synthesis, click the layout icon in libero ide to invoke designer. corecfi requires no special place-and-route settings. corecfi handbook v2.0 11 3 interface description parameters corecfi has parameters (verilog) and generics (vhdl), described in table 3-1 , for configuring the rtl code. all parameters and generics are integers. signals the port signals for the corecfi macro are defined in table 3-2 on page 12 and illustrated in figure 3-1 . corecfi has 187 i/o signals. the user will need to create the device d pin by instantiating tristate i/o pads using the dq_oe_n signal and the corecfi dq_in and dq_out signals. this core is typically used with external device package pins (a, d, ce_n, oe_n, we_n, rp_n, byte_n, word_n, and ry_by_n as i/o pads a total of 57 external i/os), and it does not directly instantiate the flash memory, thou gh it does interface with the flash memory, as shown in figure 2 on page 6 (flash memory interface signals begin with fm_?). the user instantiates the flash memory with the smartgen software tool provided within libero ide. figure 3-1 corecfi i/o signal diagram table 3-1 corecfi paramet er/generic descriptions parameter values description family 0 to 99 must be set to match the supported fpga family: 17 C fusion size integer 6 to 18 indicates the number of address bits used by corecf i (i.e., the size of the fusion flash memory accessed by corecfi e.g., 10=1kb, 12=4kb, 16=64kb, 18=256kb). dq_out[31:0] ry_by_n dq_oe_n byte_n word_n a[17:0] dq_in[31:0] ce_n oe_n we_n rp_n clk fm_busy fm_data_out[31:0] fm_status[1:0] fm_read fm_write fm_program fm_erase_page fm_overwrite_protect fm_unprotect_page fm_discard_page fm_spare_page fm_page_status fm_address[17:0] fm_data_in[31:0] fm_data_width[1:0] interface description 12 corecfi handbook v2.0 table 3-2 corecfi i/o signal descriptions name type description word_n byte_n inputs active low. controls the data width used by corecfi: word_n, byte_n x0 = 8-bit mode dq_in/out[7:0] active 01 = 16-bit mode dq_in/out[15:0] active 11 = 32-bit mode dq_in/out[31:0] active a[17:0] input address inputs during read and write operat ions. the a[0] input is ignored in 16-bit mode a[1] becomes the lowest-order address in 16-bit mode. the a[1:0] bits are ignored in 32-bit mode a[2] becomes the lowest-order address in 32-bit mode (see the word_n, byte_n description). dq_in[31:0] input data input pins during any write operatio n. dq_in[31:8] are ignored in 8-bit mode; dq_in[31:16] are ignored in 16-bit mode. the user should connect this to the receiver side of the cfi d bidirectional pads. ce_n input corecfi is selected when ce_n is asserted. this signal is active low and must be asserted for reads or writes to be executed. oe_n input dq_out[31:0] will be enabled onto the external cfi databus when ce_n and oe_n are both asserted (assuming the user has used the dq_oe_n signal as the active low output enable for the dq_out pads see the dq_oe_n description). this signal is active low. we_n input writes to corecfi will be enabled when ce_n and we_n are both asserted. writes are ignored if ce_n or we_n is not asserted. writes take one clock cycle to execute. the actual command is executed on the clock edge following the we_n sample. at the end of a write, both ce_n and we_n need to be synchronously deasserted. this signal is active low. rp_n input active low asynchronous reset. this signal rese ts the state of corecfi when asserted. it is recommended that this signal not be asserted while ry_by_n is asserted; otherwise, the fusion flash memory device may be damaged. reset places corecfi in read array mode, sets the status to 80h (ready), and tristates the data pins. dq_out[31:0] output data output pins during any read operatio n. dq_out[31:8] are unused in 8-bit mode; dq_out[31:16] are unused in 16-bit mode. the user should use this as the driver to the cfi d bidirectional pads. dq_oe_n output active low enable for the dq_out pins. the user should use this signal as the active low output enable for the cfi d bidirectional pa ds. this signal is as serted when ce_n and oe_n are both asserted. note: all signals are active high (logic 1) unless otherwise noted. signals corecfi handbook v2.0 13 ry_by_n output active low busy signal. when asserted, indicates that the fusion flash memory is performing a write operation. this signal is no t asserted during a read operation. it is the user's responsibility to hold ce_n low for some period of time while the read data becomes valid. the latency will be lower for consecutive same-page accesses and larger for new read operations or cross-page-boundary accesses. typical timings are 2 clock cycles and 5 clock cycles, respectively, for the above read operations. alternatively, the user can monitor the fusion memory fm_busy signal, which is asserted during a read operation. refer to the fusion family of mixed-signal flash fpgas datasheet for specific timing information on reading data from the flash memory. clk input flash memory interface clock. all operations an d status are synchronous to the rising edge of this clock signal. note that corecfi synchronizes the asynchronous inputs using this clock. fm_busy input when asserted, indicates that the fusion flash memory is performing an operation. fm_data_out[31:0] input data returned from the fusion flash memory during a read fm_status[1:0] input status of the last operation completed fm_read output when asserted, this signal initiates a flash memory read operation. fm_write output when asserted, this signal initiates writin g the value present on the fm_data_in[31:0] outputs to the assembly buffer of the flash memory within the fusion device. fm_program output when asserted, this signal causes the contents of the assembly buffer to be written into the addressed cell array page in the flash memory within the fusion device. fm_erase_page output when asserted, the addressed page is erased (all zeroes). fm_overwrite_protect output when asserted, all program operations will set the overwrite protect bit of the page being programmed. fm_unprotect_page output when asserted, the page addressed is copied in to the page buffer, and the page buffer is made writable. fm_discard_page output when asserted, the contents of the page buffer are discarded so a new page write can be started. fm_spare_page output when asserted, the sector addressed is used to access the spare page within that sector. fm_page_status output when this signal is asserted during a read, it indicates that the status for the currently addressed page is being accessed. fm_address[17:0] output these output signals are used as the byte offset in the cell array, ass embly buffer, or special function register interface within the fusion flash memory. table 3-2 corecfi i/o signal descriptions (continued) name type description note: all signals are active high (logic 1) unless otherwise noted. interface description 14 corecfi handbook v2.0 fm_data_in[31:0] output data to be written to the fusion flash memory fm_data_width[1:0] output these output signals are used to select the data width mode of the fusion flash memory: 00 = 1 byte in fm_data_in/out[7:0] active 01 = 2 bytes in fm_data_in/out[15:0] active 10 = 4 bytes in fm_data_in/out[31:0] active 11 = 4 bytes in fm_data_in/out[31:0] active table 3-2 corecfi i/o signal descriptions (continued) name type description note: all signals are active high (logic 1) unless otherwise noted. corecfi handbook v2.0 15 4 supported cfi commands corecfi supports the read query, read, automatic erase, automatic write, lock, and status cfi operations. the command descriptions are summarized in table 4-1 . the bus cycles are defined in figure 4-1 on page 16 , figure 4-2 on page 21 , and figure 4-3 on page 22 . table 4-1 command descriptions command no. of bus cycles first bus cycle second bus cycle notes operation address data operation address data read query 2 write x 98h read qa qd 1 read id codes 2 write x 90h read ia id read array 1 or 2 write x ffh read aa ad 2 read status 2 write x 70h read x sd clear status 1 write x 50h erase page 2 write pa 20h write pa d0h 3 single write 2 write x 40h write aa ad 4 multi-write 2 write pa e8h write pa n 5, 6 page lock 2 write x 60h write pa 01h 7 page unlock 2 write x 60h write pa d0h legend: x = any address within the device qa = query address qd = query data ia = identifier address id = identifier data a = array address ad = array data sd = status data pa = any address within the page notes: 1. the read query does not require the address to be 55h. 2. the write portion of the read array command is only needed if not already in read array mode. 3. the erase page operation will fail if the page is locked. 4. the page portion of the address is ignored for the second bus cycle. 5. the page specified by aa is the page the data will be writte n to. the page portion of the address is ignored once the multi- write command has been sent (note that this means that writes will wrap around onto the same current page if the page address goes outside the pa specified with the first bus cycle). 6. n is the number of elements (bytes / words / double words), mi nus one, to be written to the write buffer. expected count rang es are n = 00h to n = 7fh (e.g., 1 to 128 bytes) in 8-bit mode, n = 00h to n = 003fh in 16-bit mode, and n = 00h to n = 1fh in 32-bit mode. bus cycles 3 and higher ar e for writing data into the write buffer. the confirm command (d0h) is expected after exactly n + 1 write cycles; any other command at that point in the sequence will prevent the transfer of the buffer to the array (the write will be aborted). 7. locking a page prevents erasing or writing new data to the page. 8. all new commands are ignored while the device is busy. supported cfi commands 16 corecfi handbook v2.0 read corecfi read operations, other than read array, are always preceded by a write command to set up the read sequence. a preceding write is only required for the read array oper ation when the device is not already in read array mode. during read operations, ce_n and oe_n must be assert ed, and we_n and rp_n must be deasserted. the fusion flash memory device contains a 16-byte read page buffer that enables fast data transfers. write all corecfi operations, other than read array, are always preceded by a write command to set up the read sequence. a preceding write is only required for the read array operat ion when the device is not already in read array mode. during write operations, ce_n and we_n must be asserted, and oe_n and rp _n must be deasserted. read query command the read query command causes corecfi to load the query database from a spare page in the fusion flash memory. the algorithm for the read query command is shown in figure 4-1 . the query data for core cfi largely follows the intel format and is summarized in table 4-2 on page 17 through table 4-5 on page 19 . query data is always supplied on the least significant 8 bits d[7:0]. the address of the query data starts at 10h, 20h, or 40h in 32-bit, 16-bit, or 8-bit mode, respectively. the spare page address will be specified by the smartgen tool through the use of the query_page generic/parameter. the smartgen tool will also generate the query data to be stored in the specified spare page. figure 4-1 corecfi read query flow diagram start write command read query (0x98) to any address read from query address query data will be returned finished reading query data? read query complete yes no read query command corecfi handbook v2.0 17 table 4-2 cfi qu ery identification offset [17:2] offset [17:1] offset [17:0] length (bytes) description hex data notes 0x00 0x00 0x00 1 manufacturer code 0x5a 0x01 0x02 0x04 1 device size code size set to hex representation of size generic 0x010 0x011 0x012 0x020 0x022 0x024 0x040 0x044 0x048 3 query-unique ascii string qry 0x51 0x52 0x59 q r y 0x013 0x014 0x026 0x028 0x04c 0x050 2 primary algorithm command set and control interface id code 16-bit id code defining a specific algorithm (refer to jep137) 0x00 0x00 no command set specified 0x015 0x016 0x02a 0x02c 0x054 0x058 2 address for primary algorithm extended query, table 4-5 on page 19 address 0000h means that no extended table exists. 0x31 0x00 table at offset 0x0031 0x017 0x018 0x02e 0x030 0x05c 0x060 2 alternative algorithm command set and control interface id code second specific algorithm supported by the device (refer to jep137) id code = 0000h means that no alternate algorithm is employed. 00x00 0x00 no alternate command set exists in device. 0x019 0x01a 0x032 0x034 0x064 0x068 2 address for alternative algorithm extended query, table 4-6 on page 21 address 0000h means that no alternate extended table exists. 0x00 0x00 no alternate extended query exists in device. supported cfi commands 18 corecfi handbook v2.0 table 4-3 cfi query syste m interface information offset [17:2] offset [17:1] offset [17:0] length (bytes) description hex data notes 0x01b 0x036 0x06c 1 v cc logic supply minimum program/erase or write voltage bits 7 C 4: bcd value in volts bits 3 C 0: bcd value in hundreds of millivolts 0x30 3.0 v 0x01c 0x038 0x070 1 v cc logic supply maximum program/erase or write voltage bits 7 C 4: bcd value in volts bits 3 C 0: bcd value in hundreds of millivolts 0x36 3.6 v 0x01d 0x03a 0x074 1 v pp (programming) supply minimum program/erase voltage bits 7 C 4: hex value in volts bits 3 C 0: bcd value in hundreds of millivolts 0x00 0.0 v C no v pp pin 0x01e 0x03c 0x078 1 v pp (programming) supply minimum program/erase voltage bits 7 C 4: hex value in volts bits 3 C 0: bcd value in hundreds of millivolts 0x00 0.0 v C no v pp pin 0x01f 0x03e 0x07c 1 typical timeout per single byte/word/dword program, 2 n s (if supported; 00h = not supported) 0x14 16 ms 0x020 0x040 0x080 1 typical timeout for maximum-size multi-byte program, 2 n s (if supported; 00h = not supported) 0x14 16 ms 0x021 0x042 0x084 1 typical timeout per individual block erase, 2 n m s (if supported; 00h = not supported) 0x04 16 ms 0x022 0x044 0x088 1 typical timeout for full chip erase, 2 n (if supported; 00h = not supported) 0x00 not supported 0x023 0x046 0x08c 1 maximum timeout for byte/word/dword program, 2 n times typical (offset 1fh) (00h = not supported) 0x01 32 ms 0x024 0x048 0x090 1 maximum timeout for multi-byte program, 2 n times typical (offset 20h) (00h = not supported) 0x01 32 ms 0x025 0x04a 0x094 1 maximum timeout per individual block erase, 2 n times typical (offset 21h) (00h = not supported) 0x01 32 ms 0x026 0x04c 0x098 1 maximum timeout for chip erase, 2 n times typical (offset 22h) (00h = not supported) 0x00 not supported read query command corecfi handbook v2.0 19 table 4-4 cfi query device geometry definitions offset [17:2] offset [17:1] offset [17:0] length (bytes) description hex data notes 0x027 0x04e 0x09c 1 device size = 2 n in number of bytes 0x12 262,144 bytes 0x028 0x029 0x050 0x052 0x0a0 0x0a4 2 flash device interface code description (refer to jep137) 0x02 0x00 16/8 async, but also supports 32 0x02a 0x02b 0x054 0x056 0x0a8 0x0ac 2 maximum number of bytes in multi-byte program = 2 n 0x07 0x00 128 bytes 0x02c 0x058 0x0b0 1 number of erase block regions within device. bits 7:0 = x = number of erase block regions x = 0 means no erase blocking, i.e., the device erases at once in bulk. x specifies the number of regions within the device containing one erase block region. x01 symmetrically blocked regions 0x02d 0x02e 0x02f 0x030 0x05a 0x05c 0x05e 0x060 0x0b4 0x0b8 0x0bc 0x0c0 4 erase block region information bits 31:16 = z, where the erase block(s) within this region are z 25 bytes in size. the value z = 0 is used for 128-byte block size. bits 15:0 = y, where y + 1 = number of erase blocks of identical size within the erase block region 0x00 0x00 0xff 0x07 128-byte regions 2,048 erase block regions table 4-5 cfi primary vendor-specific extended query offset [17:2] offset [17:1] offset [17:0] length (bytes) description hex data notes 0x031 0x032 0x033 0x062 0x064 0x066 0x0c4 0x0c8 0x0cc 3 primary algorithm extended query table; unique ascii string pri 0x50 0x52 0x49 p r i 0x034 0x068 0x0d0 1 major version number, ascii 0x31 1 0x035 0x06a 0x0d4 1 minor version number, ascii 0x31 1 0x036 0x037 0x038 0x039 0x06c 0x06e 0x070 0x072 0x0d8 0x0dc 0x0e0 0x0e4 4 optional feature and command support (1 = yes, 0 = no) bits 9 C 3 are reserved; undefined bits are 0. if bit 31 is 1, another 31-bit field of optional features is at the end of the bit 30 field. bit 0: chip erase supported = no = 0 bit 1: suspend erase supported = no = 0 bit 2: suspend program supported = no = 0 bit 3: legacy lock/unlock supported = no = 0 bit 4: queued erase supported = no = 0 bit 5: instant individual block locking supported = no = 0 bit 6: protection bits supported = no = 0 bit 7: page mode read supported = yes = 1 0x80 0x00 0x00 0x00 page mode read supported supported cfi commands 20 corecfi handbook v2.0 0x03a 0x074 0x0e8 1 supported functions after suspend: read array, status, query. other supported operations: bits 1C7: reserved; undefined bits are 0. bit 0: program supported after erase suspend = yes = 1 0x00 no suspend 0x03b 0x03c 0x076 0x078 0x0ec 0x0f0 2 block status register mask, 16 bits; active bits are 1; undefined bits are 0. 0x00 0x00 no block status 0x03d 0x07a 0x0f4 1 v cc logic supply highest performance program/erase voltage bits 0 C 3: bcd value in hundreds of millivolts bits 4 C 7: bcd value in volts 0x33 3.3 v 0x03e 0x07c 0x0f8 1 v pp optimum program/erase supply voltage bits 0 C 3: bcd value in hundreds of millivolts bits 4 C 7: hex value in volts 0x00 0.0 v C no v pp pin 0x03f 0x07e 0x0fc 1 number of protection register fields in jedec id space 0x01 no protection registers 0x040 0x041 0x042 0x043 0x080 0x082 0x084 0x086 0x100 0x104 0x108 0x10c 4 protection description bits 0 C 7: lock/bytes jedec-plane physical low address bits 8 C 15: lock/bytes jedec-plane physical high address bits 16 C 23: n such that 2 n = factory pre-programmed bytes bits 24 C 31: n such that 2 n = user-programmable bytes 0x00 0x00 0x00 0x00 no protection registers are supported. 0x044 0x088 0x110 1 page mode read capability. number of read page bytes = 2 n in number of bytes 0x04 16 bytes 0x045 0x08a 0x114 1 number of synchronous mode read configuration fields that follow 0x00 no sync burst 0x046 0x08c 0x118 1 reserved for future use 0x00 C table 4-5 cfi primary vendor-spe cific extended query (continued) offset [17:2] offset [17:1] offset [17:0] length (bytes) description hex data notes read id codes command corecfi handbook v2.0 21 read id codes command the algorithm for the read id command is shown in figure 4-2 . the identifier codes returned are either values stored in the query data spare page or the lock status of a page in the flash array. figure 4-2 corecfi read id codes flow diagram table 4-6 cfi id entifier codes offset [17:2] offset [17:1] offset [17:0] length (bytes) description notes 0x00 0x00 0x00 1 manufacturer code 1 0x01 0x02 0x04 1 device size code 2 ba+0x03 ba+0x04 ba+0x08 1 page lock status 3 notes: 1. manufacturer code default value is 0x5a. 2. device size code is the hex representation of the size generic. for example, the devi ce size code is 0x08 for a 256-byte devi ce and is 0x12 for a 256 kb device. 3. ba = the base address of the page for which to return status. for example, 0x00080 is the base address for page 1, so address 0x00088 would return the page lock status for page 1, in byte mode. the page lock status is re turned on dq[0] with the other data bits undefined. dq[0] = 0: the page is unlocked. dq[0] = 1: the page is locked. write command read identifier codes (0x90) to any address start read from identifier code address identifier code data will be returned finished reading identifier codes? read identifier codes complete yes no supported cfi commands 22 corecfi handbook v2.0 read array command the algorithm for the read command is shown in figure 4-3 . corecfi comes out of reset in read array mode, and the read array command is not required to read the array after reset. figure 4-3 corecfi read array flow diagram write command read array (0xff) to any address read from array address array data will be returned finished reading array data? read array complete yes no start read status command corecfi handbook v2.0 23 read status command the algorithm for the read status command is shown in figure 4-4 . the status register can be read to determine the success of write, page erase, or lock page commands. af ter writing the read status command, all subsequent read operations put out data from the status register until another valid command is written. the status is updated automatically when oe_n is toggled high. when error conditio ns cause status register bits s5, s4, or s3 to be set, they can only be reset by the clear status command. figure 4-4 corecfi read status flow diagram table 4-7 status register status bit description s7 busy C indicates corecfi is currently performing a command and is not complete: 0 = busy, 1 = ready s6 tbd s5 erase and clear lock bit status 1 = error in page erase or clear page lock bit 0 = successful page erase or clear page lock bit once set, this bit can only be cleared by a clear status command. s4 write and set page lock bit status 1 = error in write or set page lock bit 0 = successful write or set page lock bit once set, this bit can only be cleared by a clear status command. s3 C s2 tbd s1 device protection status 1 = page lock bit detected, operation aborted 0 = page is unlocked once set, this bit can only be cleared by a clear status command. s0 tbd start write command read status register (0x70) to any address read from any address status register will be returned as data finished reading status register? read status register complete yes no supported cfi commands 24 corecfi handbook v2.0 clear status command the algorithm for the clear status command is shown in figure 4-5 . when error conditions cause status register bits s5, s4, or s3 to be set, they can only be reset by the clear status command. figure 4-5 corecfi clear status flow diagram start write command clear status register (0x50) to any address clear status register complete erase page command corecfi handbook v2.0 25 erase page command the algorithm for the erase page command is shown in figure 4-6 . the erase page requires two bus cycles to start: the command itself and a confirm. once the erase starts, it cannot be interrupted (any subsequent commands are ignored while the erase is in progress). corecfi handles the required sequences, and the user can determine when the erase is complete by monitoring status bit s7 until busy is no longer indicated (note that the status is updated automatically, and the read status command sequence is not required). once the erase page command has completed, status bits s1 and s5 should be checked to determine if any page erase error occurred. s1 will be set if the page to be erased is locked. s5 will be set if the erase page failed. if any of the error stat us bits are set, they can only be cleared by a clear status command. figure 4-6 corecfi er ase page flow diagram start write command erase page (0x20) to page address to erase write command erase confirm (0xd0) to page address to erase read (poll) the status register or monitor the ry/by# pin status register bit 7 or ry/by# pin status register bit 1 status register bit 5 erase successful completion erase failed with protection error erase failed with programming error = 0 = 1 = 0 = 1 = 0 = 1 supported cfi commands 26 corecfi handbook v2.0 single write command the algorithm for the single write command is shown in figure 4-7 . the single write is used to write a single byte, word, or double word in 8-bit, 16-bit, or 32-bit mode. it shou ld be noted that the single writ e still results in the entire page (that the single write data is contained within) being written into memory. therefore, the user should avoid using single writes where multi-writes are more appropriate (i.e., wh en more than one location within a page is to be written). a single write is initiated by executin g the single write command followed by a write to the desired location (note that all other commands are ignored once the write is in progre ss). once the write command has completed (i.e., the status no longer indicates busy note that the status is updated automatically, and the read status command sequence is not required), status bits s1 and s4 should be checked to determ ine if any write error occurred. s1 will be set if a write is attempted on a page that is locked. s4 will be set if the write failed. if any of the error status bits are set, they can only be cleared by a clear status command. figure 4-7 corecfi sing le write flow diagram start write command setup write (0x40) to any address write data to address being programmed read (poll) the status register or monitor the ry/by# pin status register bit 7 or ry/by# pin status register bit 1 status register bit 4 write successful completion write failed with protection error write failed with programming error = 0 = 1 = 0 = 1 = 0 = 1 multi-write command corecfi handbook v2.0 27 multi-write command the algorithm for the multi-write command is shown in figure 4-8 on page 28 . the multi-write is used to write multiple bytes, words, or do uble words in 8-bit, 16-bit, or 32-bit mode . a multi-write is initiated by executing the multi-write command and waiting for the write buffer to beco me available (i.e., the status no longer indicates busy note that the status is updated automatically, and the read status command sequence is not required). status bit s1 should then be checked to make sure that it is not set due to the page being locked. once the write buffer if available, the second write with a data value of n is executed. n is the number of elements (bytes / words / double words), minus one, to be written to the write buffer the expected ranges are n = 00h to n = 7fh (e.g., 1 to 128 bytes) in 8-bit mode, n = 00h to n = 003f h in 16-bit mode, and n = 00h to n = 1fh in 32-bit mode. once n is written, the multiple writes to the desired locations within the page can be made. note that once the multi- write command has been issued, the page address for the subs equent data writes is ignored (this means that writes will wrap around onto the current page if th e page address goes outside the page address specified with the first bus cycle). once the last data value has been written, the confirm comm and (d0h) is expected after exactly n + 1 write cycles; any other command at that point in the sequence will prevent the transfer of the buffer to the array (the write will be aborted). note that all other command sequences are ignored on ce the confirm is received and the write to the array is started. once the multi-write command has completed (i.e., the status no longer indicates busy note that the status is updated automatically, and the read status command sequence is not required), status bit s4 should be checked to determine if any write error occurred. if any of the error status bits are set, they can only be cleared by a clear status command. supported cfi commands 28 corecfi handbook v2.0 figure 4-8 corecfi multi-write flow diagram number of elements written equal to element count? abort the write to buffer? write the command buffer program confirm (0xd0) to the page address read (poll) the status register or monitor the ry/by# pin status register bit 7 or ry/by# pin status register bit 4 write to buffer successful write a command other than buffer program confirm to any address write to buffer aborted (command sequence error) write to buffer failed with programming error = 0 (buffer not ready) = 1 (buffer ready) = 1 = 0 yes no = 1 = 0 yes no = 1 = 0 start write the command setup write buffer (0xe8) to the page address read status register status register bit 7 write the element count (n) to the page address write a buffer element to the device address status register bit 1 write to buffer failed with protection error page lock command corecfi handbook v2.0 29 page lock command the algorithm for the page lock command is shown in figure 4-9 . locking a page prevents erasing or writing new data to the page. the page lock command is a two-bus-cycle operation the first is the command itself, and the second specifies the page to be locked. once the page lock comman d has completed (i.e., the status no longer indicates busy), status bit s4 should be checked to determine if an error oc curred. s4 and s5 will be set if a command sequence error occurred; only s4 will be set if the page lock failed. if any of the error status bits are set, they can only be cleared by a clear status command. figure 4-9 corecfi pag e lock flow diagram start write command lock page (0x60) to any address write command lock page confirm (0x01) to page address to lock read (poll) the status register or monitor the ry/by# pin status register bit 7 or ry/by# pin status register bits 4 and 5 status register bit 4 lock successful completion lock failed with command sequence error lock failed with error = 0 = 1 = 11 = 0 = 1 = 0 supported cfi commands 30 corecfi handbook v2.0 page unlock command the algorithm for the page unlock command is shown in figure 4-10 . unlocking a page enables erasing or writing new data to the page. the page unlock command is a two-bus-cycle operation the first is the command itself, and the second specifies the page to be unlocked. once the page unlock command has completed (i.e., the status no longer indicates busy), status bit s5 should be checked to determine if an error occurred. s4 and s5 will be set if a command sequence error occurred; only s5 will be set if the page unlock failed. if any of the error status bits are set, they can only be cleared by a clear status command. figure 4-10 corecfi page unlock flow diagram start write command unlock page (0x60) to any address write command unlock page confirm (0xd0) to page address to unlock read (poll) the status register or monitor the ry/by# pin status register bit 7 or ry/by# pin status register bit 4 and 5 status register bit 5 unlock successful completion unlock failed with command sequence error unlock failed with error = 0 = 1 = 11 = 0 = 1 = 0 timing diagrams corecfi handbook v2.0 31 timing diagrams an example write waveform is shown in figure 4-11 . note that the device will become busy for an extended time for any writes that require a write to the device array. figure 4-11 corecfi write waveform 8 9 10 11 12 13 14 a1 d1 s n s n+1 s n+2 123456789 a0 a1 d0 d1 clk ce_n we_n a d oe_n ry_by_n clk ce_n we_n a d oe_n ry_by_n supported cfi commands 32 corecfi handbook v2.0 an example write followed by a read is shown in figure 4-12 . figure 4-12 corecfi write C read waveform 12345678 a w d w clk ce_n we_n a d oe_n ry_by_n 7 8 9 101112131415 a r d r clk ce_n we_n a d oe_n ry_by_n timing diagrams corecfi handbook v2.0 33 an example read waveform, which crosse s a read page boundary, is shown in figure 4-13 . note that a bx to a by represents a transition from one read page to another, and thus, the subsequent output data d by 0 (associated with a by 0) takes longer to become valid due to the time required to load the 16-byte read page buffer with the new page data. figure 4-13 corecfi read waveform 12345678910111213141516 clk ce_n oe_n a[17:4] a[3:0] d ry_by_n we_n a bx 0 a bx d bx 0 a bx 1 a bx 2 d bx 1 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 a bx 2 d bx 2 a by 0 a by d by 0 a by 1 d by 1 clk ce_n oe_n a[17:4] a[3:0] d ry_by_n we_n corecfi handbook v2.0 35 5 implementation hints this chapter provides various hints to ease the process of implementation and integration of corecfi into your own design. usage with internal flash memory proper operation of the corecfi design requires the use of the fusion flash memory. the fusion flash memory is an integral part of the corecfi design corecfi will not function properly without it. corecfi provides a transparent interface to the flash memory that should not be modified; corecfi should be connected to the flash memory as shown in the user testbench file corecfi_chip.v (or corecfi_chip.vhd ) located in the coreconsole/corecfi/rtl/ implementation hints 36 corecfi handbook v2.0 09 00000000 00 0a 00000000 00 0b 00000000 00 0c 00000000 00 0d 00000000 00 0e 00000000 00 0f 00000000 00 10 01010001 51 11 01010010 52 12 01011001 59 13 00000000 00 14 00000000 00 15 00110001 31 16 00000000 00 17 00000000 00 18 00000000 00 19 00000000 00 1a 00000000 00 1b 00110000 30 1c 00110110 36 1d 00000000 00 1e 00000000 00 1f 00011000 14 20 00011000 14 21 00000100 04 22 00000000 00 23 00000001 01 24 00000001 01 25 00000001 01 26 00000000 00 27 00010010 12 28 00000010 02 29 00000000 00 2a 00000111 07 2b 00000000 00 2c 00000001 01 table 5-1 default cfi id codes (continued) offset default binary value hex equivalent generating and programming the cfi query database corecfi handbook v2.0 37 when smartgen is used to generate a programming file, it also generates a memory image file and an hdl file for use in simulation. these files can be used to simulate the corecfi-based design with the desired memory initialization. refer to the smartgen users guide for details on the use of the smartgen tool. 2d 00000000 00 2e 00000000 00 2f 11111111 ff 30 00000111 07 31 01010000 50 32 01010010 52 33 01001001 49 34 00110001 31 35 00110001 31 36 10000000 80 37 00000000 00 38 00000000 00 39 00000000 00 3a 00000000 00 3b 00000000 00 3c 00000000 00 3d 00110011 33 3e 00000000 00 3f 00000001 01 40 00000000 00 41 00000000 00 42 00000000 00 43 00000000 00 44 00000100 04 45 00000000 00 46 00000000 00 table 5-1 default cfi id codes (continued) offset default binary value hex equivalent corecfi handbook v2.0 39 6 testbench operation and modification verification testbench included with all releases of corecfi is a verification testbench that verifies operation of the corecfi macro. a simplified block diagram of the verification testbench is shown in figure 6-1 . the verification test suite includes a verification testbench, a test driver, a set of test cases, and test configurations. the testbench instantiates and interconnects the dut (design under test), which is the corecfi macro; the fusion flash memory behavioral model (bmod); and the test driver. the test driver is used to provide an interface shell between the testbench and individual test cases (note that the testbench is a common testbench for all test cases i.e., the testbench does not change from test to test). for each test case, there is a specific test configuration that associates the test case with the test driver. note that there are a number of test cases that must be run to fully verify the corecfi ip; this can be done by running the runsim.do file. figure 6-1 corecfi verification testbench the source code for the verification testbench is only available with the corecfi rtl release. a compiled model sim simulation is available with the ob fuscated and evaluation releases. flash memory initialization file test configuration fusion flash memory bmod testbench corecfi test driver test case test result (log file) testbench operation and modification 40 corecfi handbook v2.0 verification tests corecfi is verified through a number of tests that exercise corecfi through the external interface. the corecfi verification testbench uses the fusion flash memory behavioral model to simulate the behavior of the flash memory in fusion devices. the memory behavioral model is provided (as a library cell) as part of libero ide for all actel fusion products. the verification testbench includes test procedures to check the following cfi operations: ? read, read query, and read id codes ? single write and multi-write ? read and clear status ? page lock and unlock ?erase page simple application testbench an example user testbench is included with the evaluati on, obfuscated, and rtl releases of corecfi. the user testbench is provided in precompiled model sim format and in rtl source code for all releases (evaluation, obfuscated, and rtl) for you to examine and modify to suit your needs. the source code for the user testbench is provided to ease the process of integrating the corecfi macro into your desi gn and verifying according to your own custom needs. a block diagram of the user testbench is shown in figure 6-2 . figure 6-2 corecfi user testbench the user testbench includes a simple example design that se rves as a reference for users who want to implement their own designs. the testbench for the example user design implements a subset of the functionality tested in the verification testbench, described in the previous chapte r. conceptually, as shown in figure 6-2 , corecfi is instantiated together with a behavioral microcontroller that controls the operation of co recfi via reads and writes to access internal registers. once you have familiarized yourself with the hdl source code for the user testbench, you may wish to customize, recompile, and run the simulation, as described in the interface description on page 11 . cfi command generator and response checker fusion flash memory bmod corecfi user testbench corecfi handbook v2.0 41 a vhdl testbench support routines the verification testbench for the corecfi macro makes use of several support routines. the support routines are described in this appendix for the vhdl verification testbench. the vhdl support routines (procedures and functions) ar e provided within a package. the support routines are referenced from within the verification testbench, via library and use clauses. to include these routines in a custom testbench, add the following two lines: library corecfi_lib; use corecfi_lib.corecfi_pkg.all; a brief description of the support routines is given below. cfi_erase perform the cfi erase page operation to erase a page in the flash memory and wait for busy to deassert. cfi_single_write perform the cfi single write command to write a single location in the flash memory and wait for busy to deassert. cfi_multi_write perform the cfi multi-write command to initiate a cfi multiple write command. the parameter write_count must be set to the number of data elements to be written, minus one. the buffer_write procedure must be used after this to fill the internal buffer and initiate the program. cfi_change_lock perform the cfi lock page or unlock page command to protect or unprotect a page in the flash memory. the parameter lock should be set to true to protect the page or to false to unprotect the page. cfi_clear_status perform the cfi clear status command to clear any latched bits in the status register. cfi_read_status perform the cfi read status command to enter the read status mode. use the procedure flash_read for the actual data reads. cfi_read_id perform the cfi read id codes command to enter the read id codes mode. use the procedure flash_read for the actual data reads. cfi_read_array perform the cfi read array command to enter the read array mode. use the procedure flash_read for the actual data reads. cfi_read_querry perform the cfi read query command to enter the read query mode. use the procedure flash_read for the actual data reads. proc_write write a data value to the cfi interface. this is used by the higher-level cfi procedures to write data to the cfi interface. init_flash initialize the cfi interface and wait for busy to deassert. flash_read read a data value from the cfi interface and verify the returned data. the parameter data_in contains the expected value for the verification. used after the cfi_read_* procedures to read the data from the cfi. flash_read_status read the status data from the cfi interface. the parameter expect_data contains the expected value for the verification, and the parameter expect_mask selects the bits to be verified (a "1" in the mask for a bit position selects the bit for verification). note that the device must be in read status mode before using this procedure. buffer_write fill the cfi buffer with data for a multiple write. note that the cfi_multi_write command must be used prior to this to initiate the multiple write. cfi_poll_busy used within other procedures to poll busy while waiting for a command to complete. corecfi handbook v2.0 43 b product support actel backs its products with various support services including customer service, a customer technical support center, a web site, an ftp site, electronic mail, and worldw ide sales offices. this append ix contains info rmation about contacting actel and usin g these support services. customer service contact customer service for non-technical product support , such as product pricing, product upgrades, update information, order status, and authorization. from northeast and north central u.s.a., call 650.318.4480 from southeast and southwest u.s.a., call 650. 318.4480 from south central u.s.a., call 650.318.4434 from northwest u.s.a., call 650.318.4434 from canada, call 650.318.4480 from europe, call 650.318.4252 or +44 (0) 1276 401 500 from japan, call 650.318.4743 from the rest of the world, call 650.318.4743 fax, from anywhere in the world 650.318.8044 actel customer technical support center actel staffs its customer technical support center with highly skilled engineers who can help answer your hardware, software, and design questions. the customer technical support center spends a great deal of time creating application notes and answers to faqs. so, before you contact us, please visi t our online resources. it is very likely we have already answered your questions. actel technical support visit the actel customer support website ( www.actel.com/custsup/search.html ) for more information and support. many answers available on the searchable web resource includ e diagrams, illustrations, and links to other resources on the actel web site. website you can browse a variety of technical and non-technical information on actels home page , at www.actel.com . contacting the customer technical support center highly skilled engineers staff the technical support center from 7:00 a . m . to 6:00 p . m ., pacific time, monday through friday. several ways of co ntacting the center follow: email you can communicate your technical questions to our email address and receive answers back by email, fax, or phone. also, if you have design problems, you can email your design files to receive assistance. we constantly monitor the email account throughout the day. when sending your request to us, please be sure to include your full name, company name, and your contact information for effi cient processing of your request. the technical support email address is tech@actel.com . product support 44 corecfi handbook v2.0 phone our technical support center answers all calls. the center retrieves information, such as your name, company name, phone number and your question, and then issues a case n umber. the center then forwards the information to a queue where the first available application engineer receives the data and returns your call. the phone hours are from 7:00 a . m . to 6:00 p . m ., pacific time, monday through friday. the technical support numbers are: 650.318.4460 800.262.1060 customers needing assistance outside the us time zones can either contact technical support via email ( tech@actel.com ) or contact a local sales office. sales office listings can be found at www.actel.com/contact/offices/index.html . corecfi handbook v2.0 45 a actel electronic mail 43 telephone 44 web-based technical support 43 website 43 b block diagram 5 c common flash interface (cfi) 5 commands 15 clear status 24 erase page 25 multi-write 27 page lock 29 page unlock 30 read 16 read array 22 read id 21 read query 16 read status 23 single write 26 write 16 id codes 35 query database 35 compatibility 7 , 15 configuration 5 contacting actel customer service 43 electronic mail 43 telephone 44 web-based technical support 43 coreconsole 9 customer service 43 d device utilization and performance 6 e evaluation version 9 f features 7 functional description 7 i interfaces 11 internal flash memory, usage 35 l libero integrated design environment (ide) 10 licenses 9 evaluation 9 obfuscated 9 rtl 9 m memory, internal 35 o obfuscated version 9 overview 5 p parameters 11 place-and-route 10 product support 43 ? 44 customer service 43 electronic mail 43 technical support 43 telephone 44 website 43 q query database 35 r rtl version 9 s signals 11 simulation 10 synthesis 10 t technical support 43 testbenches 39 support routines 41 index 46 corecfi handbook v2.0 index user 40 verification 39 timing diagrams 31 read 33 write 31 writeCread 32 typical application 6 u user testbench 40 v verification testbench 39 versions evaluation 9 obfuscated 9 rtl 9 w web-based technical support 43 for more information about ac tel?s products, visit our webs ite at http://www.actel.com actel corporation ? 2061 stierlin court ? mountain view, ca 94043 usa customer service: 650.318.1010 ? customer applications center: 800.262.1060 actel europe ltd . ? river court, meadows business park ? station approach, blackwater ? camb erley surrey gu17 9ab ? united kingdom phone +44 (0) 1276 609 300 ? fax +44 (0) 1276 607 540 actel japan ? exos ebisu bldg. 4f ? 1-24-14 ebis u shibuya-ku ? tokyo 150 ? japan phone +81.03.3445.7671 ? fax +81.03.3445.7668 ? www.jp.actel.com actel hong kong ? suite 2114, two pacific place ? 88 queensway, admiralty hong kong phone +852 2185 6460 ? fax +852 2185 6488 ? www.actel.com.cn 50200094-0 /3.07 |
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